1. Field of the Invention
The present invention relates to a CAM (Content Addressable Memory) Cell Circuit which detects whether comparison data match pre-stored data or not.
2. Description of the Related Art
The most similar one to the present invention in conventional CAM Cell Circuit technologies is described by Motorola/IBM as Technical Paper 10.3 of 1955 IEEE International Solid-State Circuits Conference, and has a circuit structure shown in FIG. 1.
The conventional CAM Cell Circuit comprises a latch circuit 1 having six transistors, inverters 2, 6 having two transistors, transfer gates 3, 4 having one or two transistors, and a pull-down transistor 5. Those circuits are connected to a read/write word line R/W WL, a bit line BL, a bit line BLxe2x80x2, and comparison data lines CompD, CompDxe2x80x2.
When the read/write word line R/W WL becomes active, and then, xe2x80x9c0xe2x80x9d, and xe2x80x9c1xe2x80x9d, for example, are Input to the latch circuit 1 from the bit line BL, and the bit line BLxe2x80x2, respectively, the latch circuit 1 preserves xe2x80x9c0xe2x80x9d, the control terminal side of the transfer gate 3 becomes xe2x80x9c0xe2x80x9d, and that side of the transfer gate 4 xe2x80x9c1xe2x80x9d.
Thereafter, when xe2x80x9c0xe2x80x9d, and xe2x80x9c1xe2x80x9d are input to the latch circuit 1 from the comparison data lines CompD, CompDxe2x80x2, respectively, xe2x80x9c1xe2x80x9d of the comparison data line CompDxe2x80x2 is inverted to xe2x80x9c0xe2x80x9d by the inverter 6. At this time, as xe2x80x9c1xe2x80x9d is applied to the control terminal side of the transfer gate 4, and the gate 4 becomes conductive, xe2x80x9c0xe2x80x9d is applied to the gate of the pull-down transistor 5.
Therefore, the pull-down transistor 5 becomes off, and a match line Match xe2x80x9c1xe2x80x9d to detect that the same data as comparison data has been stored on the latch circuit 1.
In conventional CAM Cell Circuits such as the above circuit, the latch circuit 1 comprises six transistors, the inverter 2 two transistors, and the transfer gates 3, 4 one or two transistors. And one pull-down transistor is further installed. That is, the conventional CAM Cell Circuits comprise 13 or 15 transistors in total.
Therefore, there have been a problem that the conventional CAM Cell Circuits are large in the circuit area due to large number of circuit elements, and the large circuit area slows down the operation of the circuit to prevent it from keeplng-up with speeding up of processors in recent years.
The present invention is made to solve the above-mentioned drawbacks of conventional CAM Cell Circuits. The object of the present invention is to offer a CAM Cell Circuit capable of speeding up of the operation by reducing the number of circuit elements and the circuit area.
In order to achieve the above-mentioned object, a first characteristic of the present invention is as follows:
A CAM Cell Circuit has a memory cell circuit to store data, a decision circuit to decide whether comparison data match stored data on said memory cell circuit or not, and an output circuit to output a decision result made by said decision circuit to a match line, said decision circuit comprising an exclusive-OR circuit connecting in parallel a circuit having first and second transistors in series-connection, and a circuit having third and fourth transistors in series-connection: and a pre-charging circuit having a circuit connecting in series fifth and sixth transistors with different polarity from that of said first to fourth transistors, wherein stored data on said memory cell circuit, and stored data with different polarity from that of the former data are applied to each gate of said second and fourth transistors, respectively, said fifth and sixth transistors simultaneously become on to pre-charge said exclusive-OR circuit to output not-match signal to said match line by controlling said output circuit before the decision operation, and thereafter, comparison data and comparison data with different polarity from that of the former data are applied to each gate of said first and third transistors, respectively, and said exclusive-OR circuit decides whether the stored data on said memory cell circuit match the comparison data to output a match or not-match signal to said match line by controlling said output circuit based on a decision result.
A second characteristic of the present invention is as follows:
A CAM Cell Circuit has a memory cell circuit to store data, a decision circuit to decide whether comparison data match stored data on said memory cell circuit or not, and an output circuit to output a decision result made by said decision circuit to a match line, said decision circuit comprising an exclusive-OR circuit connecting in parallel a circuit having first and second transistors in series-connection, and a circuit having third and fourth transistors in series-connection; and a pre-charging circuit connecting in parallel a circuit having fifth and sixth transistors with different polarity from that of said first to fourth transistors, and a circuit having seventh and eighth transistors with different polarity from that of said first to fourth transistors, wherein stored data on said memory cell circuit, and stored data with different polarity from that of the former data are applied to each gate of said fifth and seventh transistors, respectively, stored data on said memory cell circuit and stored data with different polarity from that of the former data are applied to each gate of said second and fourth transistors, respectively, either said circuit having the fifth and sixth transistors in series-connection or said circuit having the seventh and eighth transistors in series-connection becomes on to pre-charge said exclusive-OR circuit to output not-match signal to said match line by controlling said output circuit before decision operation, and thereafter, comparison data and comparison data with different polarity from that of the former data are applied to each gate of said first and third transistors, respectively, said exclusive-OR circuit decides whether the stored data on said memory cell circuit match the comparison data to output a match or not-match signal to said match line by controlling said output circuit based on a decision result.
A third characteristic of the present invention is as follows:
A CAM Cell Circuit has a memory cell circuit to store data, a decision circuit to decide whether comparison data match stored data on said memory cell circuit or not, and an output circuit to output a decision result made by said decision circuit to a match line, said decision circuit comprising an exclusive-OR circuit having first and second transistors connected together at each drain; and a pre-charging circuit connecting in series fourth and fifth transistors with different polarity from that of said first and second transistors, wherein stored data on said memory call circuit, and stored data with different polarity from that of the former data are applied to each source of said first and second transistors, respectively, said fourth and fifth transistors simultaneously become on to pre-charge said exclusive-OR circuit to output not-match signal to said match line by controlling said output circuit before decision operation, and thereafter, comparison data and comparison data with different polarity from that of the former data are applied to each gate of said first and second transistors, respectively, and said exclusive-OR circuit decides whether the comparison data match the stored data on said memory cell circuit to output a match or not-match signal to said match line by controlling said output circuit based on a decision result.
A fourth characteristic of the present invention is as follows:
A CAM Cell Circuit has a memory cell circuit to store data, a decision circuit to decide whether comparison data match stored data on said memory cell circuit or not, and an output circuit to output a decision result made by said decision circuit to a match line, said decision circuit comprising an exclusive-OR circuit having first and second transistors connected together at each drain; and a pre-charging circuit connecting in parallel a circuit having third and fourth transistors with different polarity from that of said first and second transistors, and a circuit having fifth and sixth transistors with different polarity from that of said first and second transistors, wherein stored data on said memory cell circuit, and stored data with different polarity from that of the former data are applied to each gate of said third and fifth transistors, respectively, stored data on said memory cell circuit, and stored data with different polarity from that of the former data are applied to each source of said first and second transistors, either said circuit having said third and fourth transistors in series-connection, or said circuit having said fifth and sixth transistors in series-connection becomes on to pre-charge said exclusive-OR circuit to output not-match signal to said match line by controlling said output circuit before decision operation, and thereafter, the comparison data and the comparison data with different polarity from that of the former data are applied to each gate of said first and second transistors, respectively, and said exclusive-OR circuit decides whether the comparison data match the stored data on said memory cell circuit to output a match or not-match signal to said match line by controlling said output circuit based on a decision result.
A fifth characteristic of the present invention is as follows:
A CAM Cell Circuit has a memory cell circuit to store data, a decision circuit to decide whether comparison data match stored data on said memory cell circuit or not, and an output circuit to output a decision result made by said decision circuit to a match line, said decision circuit comprising a static-type exclusive-OR circuit configured to connect in parallel a circuit having a first transistor and a second transistor with different polarity from that of the first one in series-connection, and a circuit having a third transistor and a fourth transistor with different polarity from that of the third one in series-connection, and to have said second and third transistors connected together at each drain, further to connect the drain of said first transistor, and the source of said second transistor, and to connect the drain of said third transistor, and the source of said fourth transistor, wherein stored data on said memory cell circuit, and stored data with different polarity from that of the former data are applied to each gate of said first and second transistors, respectively, become on to make said exclusive-OR circuit pre-charge state to output not-match signal to said match line by controlling said output circuit before decision operation and thereafter, comparison data, and comparison data with different polarity from that of the former data are applied to each source of said second and third transistors, and said exclusive-OR circuit decides whether the comparison data match the stored data on said memory cell circuit or not to output a match or not-match signal to said match line by controlling said output circuit based on a decision result.
In a preferred embodiment of the invention, it is desirable that a pair of bit lines to input data to said memory cell circuit may be also used as a pair of comparison data lines to input comparison data to said exclusive-OR circuit.
In a further preferred embodiment, it is desirable that said memory cell circuit may be a latch circuit, and said output circuit may comprise a pull-down transistor to pull-down said match line to a reference potential which means not-match state.
Other and further objects and features of the present invention will become obvious upon understanding of the illustrative embodiments about to be described in connection with the accompanying drawings or will be indicated in the appended claims, and various advantages not referred to herein will occur to one skilled in the art upon employing of the invention in practice.